March Special Limited Time 60% Discount Offer - Ends in 0d 00h 00m 00s - Coupon code: 2493360325

Good News !!! EN0-001 ARM Accredited Engineer is now Stable and With Pass Result

EN0-001 Practice Exam Questions and Answers

ARM Accredited Engineer

Last Update 1 day ago
Total Questions : 210

EN0-001 is stable now with all latest exam questions are added 1 day ago. Just download our Full package and start your journey with ARM Accredited Engineer certification. All these ARM EN0-001 practice exam questions are real and verified by our Experts in the related industry fields.

EN0-001 PDF

EN0-001 PDF (Printable)
$48
$119.99

EN0-001 Testing Engine

EN0-001 PDF (Printable)
$56
$139.99

EN0-001 PDF + Testing Engine

EN0-001 PDF (Printable)
$70.8
$176.99
Question # 1

When linking with the standard C library, which library functions MUST be redefined in order to port your code to a new piece of production hardware?

Options:

A.  

Functions that are not compliant with the ISO C library standard

B.  

Functions that are not compliant with the 1985 IEEE 754 standard for binary floating-point arithmetic

C.  

Target-dependent functions which use semihosting

D.  

Functions called implicitly by the compiler

Discussion 0
Question # 2

Which events would be counted using the Performance Monitoring Unit (PMU) in order to measure the data cache efficiency of an application?

Options:

A.  

Memory read instructions, and memory write instructions

B.  

Architecturally executed instructions, and instruction fetches causing a cache line refill

C.  

Memory access instructions causing a cache line refill, and memory read and write operations causing a cache access

D.  

Memory read or write operations causing a cache access, and architecturally executed instructions

Discussion 0
Question # 3

When the software floating point emulation library is used, how will the parameters be passed to the following function?

void foo(float f1, float f2, float f3, float f4);

Options:

A.  

On the stack

B.  

In registers s0-s3

C.  

In registers d0-d3

D.  

In registers r0-r3

Discussion 0
Question # 4

A C code segment contains three calls to a function, foobar ().

This code segment is to be linked with a static library that defines foobar ().

Ignoring inlining, how many copies of foobar () will the ARM linker place in the output?

Options:

A.  

None

B.  

Always one

C.  

Always three

D.  

One or more depending on optimization level

Discussion 0
Question # 5

When the processor is executing in Thumb state, which of the following statements is correct about the values stored in R15?

Options:

A.  

Bits[31:16] are duplicated with bits[15:0]

B.  

The PC value is stored in bits[31:1] and bit[0] is treated as zero

C.  

The PC value is stored in bits[31:16] and bits[15:0] are undefined

D.  

The PC value is stored in bits[15:0] and bits[31:16] are undefined

Discussion 0
Question # 6

Which of the following properties is a required characteristic of a Symmetric Multiprocessing (SMP) system?

Options:

A.  

All processors have the same view of memory

B.  

An even number of processors is included

C.  

All processors run in the same power state

D.  

All processors switch between operating system tasks in lock-step

Discussion 0
Question # 7

Which of these processors is only available as a single core configuration?

Options:

A.  

Cortex-A5

B.  

Cortex-A8

C.  

Cortex-A9

D.  

Cortex-A15

Discussion 0
Question # 8

On an ARM processor that does not implement Security Extensions, which one of the following can be the starting address of the exception vector table?

Options:

A.  

0xFFFFFFFF

B.  

0xFFFFFFF0

C.  

0xFFFF0000

D.  

0x0000FFFF

Discussion 0
Question # 9

Capturing processor execution trace is characterized as being:

Options:

A.  

Influenced by breakpoints.

B.  

Intrusive on normal processor operation.

C.  

Inaccurate regarding code execution history.

D.  

Not intrusive on normal processor operation.

Discussion 0
Question # 10

Which of the following statements best describes a Board Support Package (BSP)?

Options:

A.  

PC interface hardware for configuring a boot monitor

B.  

Hardware specific source code needed for operating system support

C.  

A working port of Linux for a specific hardware platform

D.  

Debugging hardware and software supplied with a development board

Discussion 0
Question # 11

In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)

Options:

A.  

The time spent waiting for I/O operations

B.  

The time taken to download the program via the debugger

C.  

The time taken for memory accesses

D.  

The time taken for the CPU to execute instructions

E.  

The time taken to compile the source code

F.  

The time taken to perform instruction tracing

Discussion 0
Question # 12

An application contains three calls to an external function, foobar(), which is defined in a shared (or dynamic) library. How many copies of foobar() will the linker place in the application image?

(Ignore linker inlining)

Options:

A.  

None

B.  

Always one

C.  

Always three

D.  

One or more depending on optimization level

Discussion 0
Question # 13

The effect of clicking the Stop button in a debugger is to:

Options:

A.  

Put the processor(s) into debug state.

B.  

Force the processor to execute a BKPT instruction

C.  

Hold the processor in a Reset condition

D.  

Re-initialize the memory contents.

Discussion 0
Question # 14

On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?

Options:

A.  

This transition is not possible

B.  

Execution of an SMC instruction

C.  

Execution of an SMC instruction followed by an SVC instruction

D.  

Execution of an SVC instruction followed by an SMC instruction

Discussion 0
Question # 15

What side-effect could using a debugger to read memory contents have?

Options:

A.  

The memory contents could be set to zero

B.  

Some memory contents could be rewritten

C.  

The processor MMU pagetables could be modified

D.  

The processor cache could be cleaned or/and invalidated

Discussion 0
Question # 16

The following pseudocode sequence shows a flag being set to indicate that new data is ready to be read by another thread:

data = 123;

ready = true;

Assuming that the reader threads may execute on any other core of a multicore system, which of the following is the most efficient memory barrier to place between the two writes to prevent them being observed in the opposite order?

Options:

A.  

DSBSY

B.  

DSBST

C.  

DMBSY

D.  

DMBST

Discussion 0
Question # 17

What architecture does the ARM11 MPCore implement?

Options:

A.  

ARMv6

B.  

ARMv6K

C.  

ARMv7-A

D.  

ARMv7-A with the Multiprocessing Extensions

Discussion 0
Question # 18

Which one of these statements is TRUE about code running on final hardware without a debugger attached?

Options:

A.  

FIQ exceptions must not be taken

B.  

The instruction cache must be enabled

C.  

Global variables must be initialized to zero

D.  

The Reset Vector must reside in non-volatile memory

Discussion 0
Question # 19

A deeply embedded real-time industrial control system is missing some hard real-time interrupt deadlines. Which of the following performance analysis techniques is the most suitable for identifying which routines are causing the problem?

Options:

A.  

Use an ETM instruction trace profiler, which outputs information about the program as it runs

B.  

Add some serial logging to the software, which outputs information about the program as it runs

C.  

Add a new interrupt handler, which is triggered off a timer, and dump information about the interrupted process

D.  

Use a JTAG sample-based profiler, which periodically halts the CPU, and dumps information about the interrupted process

Discussion 0
Question # 20

Which of the following would enable the use of a symmetric multiprocessing (SMP) operating system?

Options:

A.  

A dual-core Cortex-A9 processor

B.  

A Cortex-R4 processor with a Cortex-M3 system controller

C.  

A Cortex-A8 processor with a graphics processing unit (GPU)

D.  

A uni-core Cortex-A5 processor with a digital signal processor (DSP)

Discussion 0
Question # 21

A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?

Options:

A.  

Instruction cache clean only

B.  

Instruction cache invalidate only

C.  

Data cache clean and instruction cache invalidate

D.  

Data cache invalidate and instruction cache invalidate

Discussion 0
Question # 22

Consider the following code sequence, executing on a processor which implements ARM Architecture v7-

A.  

LDR r0, [r1]

STR r0, [r2]

STR r3, [r3]

R1 points to a location in normal memory. R2 and R3 point to device memory.

Which of the following statements best describes the ordering rules which apply to this sequence?

Options:

A.  

The two writes to device memory will happen in program order, but the read can be performed out of order

B.  

The memory accesses can happen in any order

C.  

The memory accesses will happen in program order

D.  

The read to r0 and the write from r0 will happen in program order, but the write from r3 can be performed out of order

Discussion 0
Question # 23

Which one of the following statements best describes the function of vector catch logic?

Options:

A.  

It traps writes to the memory containing the vector table

B.  

It provides additional resources for debugging exception handlers

C.  

It provides configurable exception priorities on an ARM processor

D.  

It provides an improved mechanism for an application to handle exceptions

Discussion 0
Question # 24

If a 16-bit Thumb instruction causes a Data Abort, which instruction would return from the handler to the instruction after the one that caused the data abort?

Options:

A.  

SUBS P

C.  

LR

B.  

SUBS PC, LR-#4

C.  

SUBS P

C.  

LR, #6

D.  

SUBS PC, LR, #8

Discussion 0
Question # 25

Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?

Options:

A.  

R0=0x100, R1 =0x1000

B.  

R0=0x100, R1=0x1002

C.  

R0=0x101, R1=0x1002

D.  

R0=0x101. R1=0x1003

Discussion 0
Question # 26

How many bytes of stack are needed to pass parameters when calling the following function?

int foo( short arg_a, long long arg_b, char arg_c, int arg_d )

Options:

A.  

0

B.  

4

C.  

8

D.  

15

Discussion 0
Question # 27

In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)

Options:

A.  

VA == PA; No address translations; instructions and data are not cached

B.  

VA! = PA; No address translations; instructions may be cached but not data

C.  

VA == PA; Address translations take place; data may be cached but not instructions

D.  

VA == PA; No address translations; instructions may be cached but not data

Discussion 0
Question # 28

Using a lower optimization level when compiling will:

Options:

A.  

Produce faster code.

B.  

Produce smaller code.

C.  

Produce non standard-compliant code.

D.  

Produce code that might be easier to debug.

Discussion 0
Question # 29

In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?

Options:

A.  

±32MB

B.  

±4MB

C.  

±12KB

D.  

±4KB

Discussion 0
Question # 30

An ARMv7 implementation might include the VFPv4-D32 floating point extension. What does the '32' indicate?

Options:

A.  

The width of the datapath in bits

B.  

The number of double precision floating point registers implemented

C.  

The number of bits of data that can be loaded or stored at once

D.  

The number of integer operations that can be performed simultaneously

Discussion 0
Question # 31

In a symmetric multi-processing (SMP) software architecture, which of the following pairs of statements are TRUE? (Select the option in which BOTH statements are TRUE).

Options:

A.  

The roles of individual cores are determined dynamically. Each core has its own set of external peripherals.

B.  

Each core has the same view of memory and shared peripherals. Any user application, process or task can be scheduled to run on any core.

C.  

The roles of individual cores are statically determined by the system designer. Hardware must be implemented to provide cache coherency between the cores.

D.  

Each core has the same view of memory and peripherals. The roles of individual cores are statically determined by the system designer.

Discussion 0
Get EN0-001 dumps and pass your exam in 24 hours!

Free Exams Sample Questions