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EN0-001 Practice Questions

ARM Accredited Engineer

Last Update 4 days ago
Total Questions : 210

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Question # 21

A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?

Options:

A.  

Instruction cache clean only

B.  

Instruction cache invalidate only

C.  

Data cache clean and instruction cache invalidate

D.  

Data cache invalidate and instruction cache invalidate

Discussion 0
Question # 22

Consider the following code sequence, executing on a processor which implements ARM Architecture v7-

A.  

LDR r0, [r1]

STR r0, [r2]

STR r3, [r3]

R1 points to a location in normal memory. R2 and R3 point to device memory.

Which of the following statements best describes the ordering rules which apply to this sequence?

Options:

A.  

The two writes to device memory will happen in program order, but the read can be performed out of order

B.  

The memory accesses can happen in any order

C.  

The memory accesses will happen in program order

D.  

The read to r0 and the write from r0 will happen in program order, but the write from r3 can be performed out of order

Discussion 0
Question # 23

Which one of the following statements best describes the function of vector catch logic?

Options:

A.  

It traps writes to the memory containing the vector table

B.  

It provides additional resources for debugging exception handlers

C.  

It provides configurable exception priorities on an ARM processor

D.  

It provides an improved mechanism for an application to handle exceptions

Discussion 0
Question # 24

If a 16-bit Thumb instruction causes a Data Abort, which instruction would return from the handler to the instruction after the one that caused the data abort?

Options:

A.  

SUBS P

C.  

LR

B.  

SUBS PC, LR-#4

C.  

SUBS P

C.  

LR, #6

D.  

SUBS PC, LR, #8

Discussion 0
Question # 25

Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?

Options:

A.  

R0=0x100, R1 =0x1000

B.  

R0=0x100, R1=0x1002

C.  

R0=0x101, R1=0x1002

D.  

R0=0x101. R1=0x1003

Discussion 0
Question # 26

How many bytes of stack are needed to pass parameters when calling the following function?

int foo( short arg_a, long long arg_b, char arg_c, int arg_d )

Options:

A.  

0

B.  

4

C.  

8

D.  

15

Discussion 0
Question # 27

In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)

Options:

A.  

VA == PA; No address translations; instructions and data are not cached

B.  

VA! = PA; No address translations; instructions may be cached but not data

C.  

VA == PA; Address translations take place; data may be cached but not instructions

D.  

VA == PA; No address translations; instructions may be cached but not data

Discussion 0
Question # 28

Using a lower optimization level when compiling will:

Options:

A.  

Produce faster code.

B.  

Produce smaller code.

C.  

Produce non standard-compliant code.

D.  

Produce code that might be easier to debug.

Discussion 0
Question # 29

In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?

Options:

A.  

±32MB

B.  

±4MB

C.  

±12KB

D.  

±4KB

Discussion 0
Question # 30

An ARMv7 implementation might include the VFPv4-D32 floating point extension. What does the '32' indicate?

Options:

A.  

The width of the datapath in bits

B.  

The number of double precision floating point registers implemented

C.  

The number of bits of data that can be loaded or stored at once

D.  

The number of integer operations that can be performed simultaneously

Discussion 0
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